

module write_to_reg(
    input wire [6:0] op,
    input wire [2:0] funct3,
    input wire [31:0] daddr,
    input wire [31:0] drdata,
    input wire [31:0] MW_regdata_out,
    output reg [31:0] out
);

    reg [31:0] offset; //reg [4:0] offset;

    always @(*) begin
        if (op != 7'b0000011) begin
            out = MW_regdata_out;
        end else begin
            //offset = (daddr[1:0] << 3);
            case (funct3)
                /*3'b000: out = {{24{drdata[offset+7]}}, drdata[offset +: 8]};
                3'b001: out = {{16{drdata[offset+15]}}, drdata[offset +: 16]};
                3'b010: out = drdata;
                3'b100: out = {24'b0, drdata[offset +: 8]};
                3'b101: out = {16'b0, drdata[offset +: 16]};*/
                3'b000: out = {{24{drdata[7]}}, drdata[7:0]};
                3'b001: out = {{16{drdata[15]}}, drdata[15:0]};
                3'b010: out = drdata;
                3'b100: out = {24'b0, drdata[7:0]};
                3'b101: out = {16'b0, drdata[15:0]};
                default: out = 32'b0; // Handle unexpected funct3 values
            endcase
        end
    end

endmodule

